This invention relates to the field of testing integrated circuits. More particularly the invention relates to a system for determining different failure limits for various electronic characteristics of integrated circuits based on selected subsets of the integrated circuits.
Integrated circuit fabrication is an extremely complex process. Therefore, the various processes used to fabricate integrated circuits are often categorized in some manner, in order to simplify the description of the various phases of fabrication. For example, the various steps employed to create the integrated circuits while they are disposed upon a monolithic substrate is often called wafer processing. After wafer processing, the devices are tested for conformance to predicted parameters in what may be called wafer testing. After wafer testing the circuits are diced and then integrated circuits that have been binned as xe2x80x9cgoodxe2x80x9d circuits are packaged.
Typically, an individual integrated circuit on the wafer is binned as good or bad during wafer testing. The wafer testing equipment is programmed to run a regimen of tests on each integrated circuit by applying known electrical input on the electrical contact pads of the integrated circuit. The electrical response of the integrated circuit to the input is sensed and measured at the output electrical contact pads of the integrated circuit. The measured output values are compared to a set of predetermined expected output values, and if any of the measured output values violate the corresponding predetermined expected output values, such as by being either greater than or less than the predetermined expected output value as the case may be, then the integrated circuit is binned by the automated wafer tester as bad.
When the circuit is designated as bad, a drop of ink is typically placed atop the circuit by the wafer tester. After the integrated circuits are diced, the pick and place unit that removes the individual integrated circuits and places them into packages detects the ink drop on the bad integrated circuits, and skips them so that they are not placed into packages and processed further. The inked integrated circuits that are left on the dicing tape by the pick and place are then discarded.
The predetermined expected output values are typically determined by correlating output values for a large number of packaged devices. The packaged devices are tested to see whether they function properly or whether they fail prematurely. The output values for those devices that either do not function at all or fail prematurely are studied, and a predetermined expected output value is selected such that most of the devices with output values that do not violate the predetermined expected output value function properly for a desired length of time, and most of the devices with output values that do violate the predetermined expected output value either do not function properly for the desired length of time or do not function properly.
Unfortunately, this method of setting expected output values is extremely imprecise. Some of the devices that violate the predetermined expected output value function properly for the desired length of time, and some of the devices that do not violate the predetermined expected output value do not function properly for the desired length of time.
Thus, this traditional method of wafer testing and binning is extremely inflexible and does not account for the individual characteristics of an integrated circuit on the wafer. For example, the automated wafer tester has no way of knowing whether the output value received from the tested integrated circuit is a value that should be expected from the integrated circuit, based on the specific processing received by that integrated circuit. Thus, some amount of integrated circuits that are actually good are binned as bad, and some amount of integrated circuits that are actually bad are binned as good. Further, once the automated wafer tester bins an specific integrated circuit as bad and places an ink drop on it, there is no easy way to go back to and review the test data and reclaim the integrated circuit.
What is needed, therefore, is a system to bin integrated circuits in response to binning limits that are based upon expected output values that take into account specific processing received by the integrated circuits, rather than upon predetermined expected output values. Further, a system is needed that provides flexibility in binning the integrated circuits in response to the binning limits.
The above and other needs are met by a method for testing integrated circuits having associated position designations, where a predetermined set of input vectors is introduced as test input into the integrated circuits. The output from the integrated circuits in response to the predetermined set of input vectors is sensed, and the output from the integrated circuits is recorded in a wafer map, referenced by the position designations. The output from at least a subset of the integrated circuits is selected and mathematically manipulated to produce a reference value. The output for each of the integrated circuits in the selected subset is individually compared to the reference value, and graded integrated circuits within the selected subset that have output that differs from the reference value by more than a given amount are identified. A classification is assigned to the graded integrated circuits and recorded in the wafer map, referenced by the position designations for the outlier integrated circuits.
In this manner, the normal degree of variation within various subsets of integrated circuits, preferably within different regions of a wafer, is taken into account in determining which of the integrated circuits are to be assigned codes, such as failure codes, and which of the integrated circuits are to pass. In other words, variation in processing conditions across the surface of a wafer may produce a difference in various electrical characteristics of the integrated circuits across the surface of the wafer. These regional differences may result in a high degree of variance in the test values for the electrical characteristic in question. By selecting subsets of the integrated circuits for separate analysis, the variance due to processing differences across the surface of the wafer can be more fully removed, and the true outlier integrated circuits within a selected subset can be more easily identified. The graded integrated circuits identified in this manner tend to be outliers because of defects, rather than because of regional differences in processing conditions across the surface of the wafer.